AMD published its first official benchmarks for the EPYC "Venice" server line on Friday, claiming the 256-core flagship is more than twice as fast as Nvidia's Vera chip in a key throughput test. The white paper extends performance assertions made at the July launch, but the comparison rests on a configuration mismatch that makes the headline figure difficult to trust.

The numbers and the caveats

In SPEC CPU 2026 intrate, a multi-copy throughput benchmark, AMD says the 256-core 9996 scores 2.24 times the result it attributes to Vera and 2.37 times the Intel Xeon 6980P. The same chip is shown 78 percent ahead of the previous-generation 192-core EPYC 9965. For the per-core Integer Rate test, AMD compares a 96-core Venice SKU against Vera's 88 cores and claims a 20 percent advantage. Both Venice results come from July testing on GCC 15.2; the Vera numbers are taken from Nvidia's own white paper.

Compiler mismatch clouds the comparison

The per-core claim introduces a second compiler version. AMD re-ran its 96-core configuration on GCC 16.1, which adds Zen 6 support, while the Vera reference remains on GCC 15.2. GCC 16 produces faster binaries at the cost of longer compile times, a difference that can shift scores materially depending on flags and workload. Comparing across major compiler releases is not standard practice, and AMD acknowledges the Vera data comes from mixed sources. The company did not disclose the power budget for the down-cored 9996 used in the Vera matchup, though the 96-core SKU tops out at 500 watts while the 256-core part is rated for 600.

Memory bandwidth and cloud workloads

On the Stream memory-bandwidth benchmark, AMD used a 96-core slice of the 9996 at 600 watts against Phoronix's controlled Vera data. Venice leads by roughly 18 percent overall and 8 percent per core. The white paper also includes database, Java and cryptography workloads where the generational improvement over the 9965 remains the most consistent data point.

What to watch

The compiler gap means the Vera comparison is indicative at best. Independent runs on matched toolchains and power envelopes will determine whether the 20 percent per-core claim holds. Silicon availability and cloud-instance pricing will matter more than white-paper ratios once Venice reaches volume.