Micron Technology reported fiscal fourth-quarter revenue of $54.23 billion, more than quadrupling from the year-ago period, as demand for high-bandwidth memory used in AI accelerators continued to outstrip the industry's ability to supply it. The company earned $33.42 per share on a GAAP basis against a consensus of $31.61 on $51.07 billion, and guided the current quarter to $38.15 per share on $61.5 billion, well ahead of the $35.40 and $57 billion the Street had modeled.
The beat and the raise
The upside was concentrated in the top line, where sales came in $3.16 billion above expectations. Guidance implies another $7.27 billion of sequential revenue growth, a pace that would have been unthinkable before the AI infrastructure build-out rewrote the memory demand curve. Management did not break out GAAP versus adjusted figures in the release, so the headline numbers carry the full weight of the comparison.
DRAM now dominates the mix
DRAM revenue surged 343 percent year over year and now represents 73 percent of total sales, a concentration that reflects the economics of stacking memory die next to the processor. Chief Executive Sanjay Mehrotra told investors the company has a "strong roadmap for future HBM products," including what he called the industry's "first custom HBM implementation" with Nvidia. With only three suppliers capable of producing HBM at scale, pricing power has remained with the manufacturers.
The supply wall holds for now
Hendi Susanto of Gabelli Funds told CNBC he has "not heard any negative data points pointing to the memory cycle reversing toward a decline anytime soon for the foreseeable future." New fabrication capacity takes years to qualify, so the structural shortage that underpins current margins persists. The near-term trajectory is therefore a function of how fast equipment vendors can deliver tools, not of end-market demand.
The cycle always turns
History argues against permanence. Memory has always moved in violent boom-bust cycles, and the same customers paying premium prices today are already investing in architectures that reduce the memory footprint per model. When supply eventually catches up, or when inference workloads shift toward lower-bandwidth configurations, the reversion will be sharp. For now, the quarter prints; the cycle waits.